The present invention relates to a bus circuit, and more specifically, to a bus circuit which connects a first device and a second device through a transmission line.
In a conventional bus circuit of this type, an output device is connected to a receive device through a transmission line that transmits a signal.
Referring to FIG. 8, a conventional bus circuit includes an output buffer 1110 provided in an output device 1100, a receiver 1210 provided in a receive device 1200 and a transmission line 1300 which connects output buffer 1110 and receiver 1210.
In output buffer 1110, an output terminal 1112 is connected to transmission line 1300. Output buffer 1110 outputs a high logic level signal to transmission line 1300 by forming a current path between a power supply V.sub.DD and output terminal 1112. Output buffer 1110 is a complimentary metal oxide semiconductor (CMOS) inverter. Output buffer 1110 includes a positive channel metal oxide semiconductor (PMOS) transistor 1113 and a negative channel metal oxide semiconductor (NMOS) transistor 1114. PMOS transistor 1113 has a gate terminal to which an input signal is applied and is connected between power supply V.sub.DD and transmission line 1300. NMOS transistor 1114 has a gate terminal to which an input signal is applied and is connected between a ground potential GND and transmission line 1300.
In the receive device 1200, the input terminal of receiver 1210 is connected to transmission line 1300. A diode 1220 is provided between the input terminal of receiver 1210 and a power supply V.sub.dd. Diode 1220 is used for producing a proper waveform of a signal received through transmission line 1300 (hereinafter referred to as first conventional art).
On the other hand, U.S. Pat. No. 5,338,978 discloses a bus circuit in which an output buffer circuit, coupled to a low potential power supply, is connected to an output buffer circuit, coupled to a high potential power supply device, through a transmission line. When the output buffer circuit coupled to the low potential power supply is inactive, a high potential signal may appear on the transmission line driven by the output buffer circuit coupled to the high potential power supply. The bus circuit keeps a pull-up output transistor off. This prevents a current from flowing to the low potential power supply through a pull-up transistor (hereinafter referred to as second conventional art).
In the first conventional art, when power supply V.sub.DD of output device 1100 is applied and power supply V.sub.dd of receive device 1200 is not applied, and when PMOS transistor 1113 of output buffer 1110 is on, current flows from power supply V.sub.DD of output device 1100 to power supply V.sub.dd of receive device 1200. This creates a problem because receiver 1210 and diode 1220 can be destroyed if an excessive current flows.
Meanwhile, the second conventional art only addresses a problem appearing when the power supply to the buffer circuit is turned off. This causes a problem because current flowing through the buffer circuit to another device cannot be cut off when power supply is applied to the buffer circuit.